Saad Syed

Projects

A mix of lab projects alongside personal builds from my spare time and hobbies.

A matrix-vector multiplication engine implemented in SystemVerilog and deployed on FPGA.

Hardware approximation of tanh with pipelining for improved performance.

Single-cycle RV32I core built in SystemVerilog and tested with assembly programs.

A UVM testbench for a data alignment module, featuring a reusable agent class, a model, and a scoreboard. Based off a Udemy course by Cristian Slav.

A collection of CUDA mini-projects to learn GPU programming.

A custom RTOS kernel with task scheduling and memory management.

Beginner-friendly C++ command line application with custom features.

A Logisim CPU with basic arithmetic support, tested with Assembly.