saad syed

Projects

Hardware & software builds — FPGA, RTL design, and beyond.

Featured

BERT Encoder on AMD Versal Hard-NoC

BERT-style transformer encoder implemented on AMD Versal, achieving 1.5 GB/s aggregate NoC bandwidth for DDR-PL communication with 4-head self-attention via AXI-Stream and DMA pipelines.

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High-Frequency Adders on Agilex-5 FPGA

Optimized a 2048-bit adder achieving 41% frequency improvement (600→848 MHz) and 25% area reduction through automated design-space exploration of Kogge-Stone configurations.

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UVM Testbench

A UVM testbench for a data alignment module, featuring a reusable agent class, a model, and a scoreboard. Based off a Udemy course by Cristian Slav.

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GPU Suite

A collection of CUDA mini-projects to learn GPU programming.

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MVM Engine

A matrix-vector multiplication engine implemented in SystemVerilog and deployed on FPGA.

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Tanh Approximation

Hardware approximation of tanh with pipelining for improved performance.

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RISC-V Core

Single-cycle RV32I core built in SystemVerilog and tested with assembly programs.

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Real-Time Executive

A custom RTOS kernel with task scheduling and memory management.

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Shell Jr

Beginner-friendly C++ command line application with custom features.

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CPU Design

A Logisim CPU with basic arithmetic support, tested with Assembly.

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