High-Frequency Adders on Intel Agilex-5
Overview
Optimized a 2048-bit adder on Intel Agilex-5, achieving 41% higher frequency and 25% less area by closing timing with TimeQuest STA using retiming and pipelining.
Results
| Metric | Before | After | Improvement |
|---|---|---|---|
| Frequency | 600 MHz | 848 MHz | +41% |
| Area (ALMs) | 10.9K | 8.2K | −25% |
| Memory LABs | 700 | 0 | −100% |
| LAB Utilization | 1,758 | 1,211 | −31% |
Approach
- Automated a sweep of 11 configurations with Bash scripts that drive Quartus synthesis and parse timing reports to pick the best frequency–area tradeoff
- Selected the optimal Kogge-Stone grouping (M=16) from the sweep results
- Applied retiming and pipelining to close timing under TimeQuest STA
- Eliminated all memory LAB usage through optimized ALM packing
Tools
SystemVerilog, Quartus Prime Pro, TimeQuest STA, Bash, Intel Agilex-5