saad syed
FPGA Research · UWaterloo

Saad
Syed

Computer Engineering @ UWaterloo. Building high-performance digital hardware — FPGA transport-layer acceleration, RTL design, and ASIC verification.

ResumeLinkedInGitHubEmail

Technical Skills

Languages

SystemVerilogVerilogC/C++PythonAssembly (ARMv7, RISC-V)

Protocols

AXI4 / AXI4-LiteAXI-StreamPCIe / QDMASPIUART

Tools

VivadoQuartus Prime ProCocoTBGTKWaveTimeQuestGitLinux

Concepts

RTL DesignTiming ClosureCDCPipelining & RetimingFSMsUVMFormal Verification (Lean4)

Experience

University of Waterloo — Prof. Mina Arashloo
Jan 2026 – PresentWaterloo, ON

FPGA Research Assistant

University of Waterloo — Prof. Mina Arashloo

  • ▸Contributing to a protocol-agnostic FPGA transport-layer acceleration architecture on AMD Alveo U250, enabling hardware offload of multiple network protocols (TCP, RoCEv2).
  • ▸Implementing PCIe/QDMA-based host ↔ FPGA communication using AXI-Stream within the OpenNIC 250 MHz user logic, allowing applications to drive FPGA transport logic.
  • ▸Building buffering, backpressure, and request-framing logic to reliably inject host application requests into a high-throughput FPGA networking pipeline.
UW ASIC Design Team
Aug 2025 – PresentWaterloo, ON

Digital Design Team Lead — Ethernet Packet Parser

UW ASIC Design Team

  • ▸Leading a team of 15 to architect a high-throughput Ethernet packet parser from scratch, owning system architecture, RTL implementation, and block-level verification across the full design lifecycle.
  • ▸Designed multi-layer packet parsing pipeline in SystemVerilog supporting Ethernet/IP/TCP header extraction with configurable match-action rules and line-rate throughput targeting.
  • ▸Led RTL implementation and floorplanning of a cryptography accelerator, achieving 200 MHz operation at 65% FPGA resource utilization.
  • ▸Architected an ACK-based bus arbitration protocol using open-drain signaling, reducing average arbitration latency by 4 cycles under multi-client contention.
VCast Online
Jan 2025 – May 2025Dubai, UAE

Software Engineer (Co-op)

VCast Online

  • ▸Led full-stack development of a collaborative mind-map platform, enabling real-time feedback and map sharing, driving community engagement up by 25%.
  • ▸Built and deployed a SvelteKit + Node.js web app integrating Cytoscape.js graph editing, Google OAuth, JWT authentication, and access control (owner vs. viewer).
  • ▸Architected a Mongoose-based feedback system enabling structured insights on nodes, edges, and graphs — improving data access times by 18%.
Dematic
May 2024 – Aug 2024Waterloo, ON

Technical Writer (Co-op)

Dematic

  • ▸Developed comprehensive technical documentation for Dematic's mechanical and control systems, supporting integration of advanced automation technologies.
  • ▸Authored detailed user manuals for Dematic's InSights logistics software, ensuring clarity and facilitating efficient deployment across multiple industries.
  • ▸Simplified complex engineering concepts for diverse audiences, enhancing usability and efficiency.
Matrox Imaging | Zebra Technologies
Jan 2023 – Apr 2023Dorval, QC (Remote)

Technical Writer (Co-op)

Matrox Imaging | Zebra Technologies

  • ▸Documented and tested new features for Matrox Design Assistant, a flowchart-based imaging application platform.
  • ▸Collaborated with software engineers to document the Matrox Imaging Library (C API).
  • ▸Used oXygen XML to update the official company user manual and user reference distributed to clients.

Education

UWaterloo
Sep 2022 – May 2027Waterloo, ON

B.A.Sc. Computer Engineering

University of Waterloo

CoursesReconfigurable Computing (Master's Level), Real-Time Operating Systems, Digital Hardware Systems, Computer Architecture, Compilers, Embedded Microprocessor Systems