FPGA Engineer · ArchES Computing
SaadSyed
Computer Engineering @ UWaterloo. Building high-performance digital hardware — low-latency FPGA design, RTL & HLS, timing closure, and ML accelerator kernels.
Technical Skills
Languages
SystemVerilogVerilogC/C++PythonVitis HLSAssembly (ARMv7, RISC-V)
Protocols
AXI4 / AXI4-LiteAXI-StreamPCIeEthernetSPIUART
Tools
Vivado (synthesis, STA, P&R)Quartus Prime ProCocoTBGTKWaveGitLinux
Concepts
RTL DesignHLSTiming ClosureLow-Latency DesignCDCDMAPipelining & Retiming
Experience
Sep 2026 – PresentToronto, ON
FPGA Engineer (Co-op)
ArchES Computing Systems
- ▸Integrated an AXI-Stream monitor into a large order-routing platform on a Xilinx V80LL and closed timing (WNS −1.77 ns → +0.049 ns), using the Vivado timing analyzer and block diagram viewer to trace critical paths and combinational loops.
- ▸Broke combinational loops with register slices and split a reset driving 30+ debug probes across two reset blocks — on a platform where full builds took about a day.
- ▸Designed the architecture of a packet capture tool and implemented it in Vitis HLS; it records packets from Ethernet RX or an exchange simulator and streams them to the host over an HMQ ring for PCAP generation, speeding up error reproduction across 10+ platforms.
Jan 2026 – Aug 2026Waterloo, ON
FPGA Research Assistant
University of Waterloo — Prof. Mina Arashloo
- ▸Built components of a protocol-agnostic FPGA transport-layer acceleration architecture on AMD Alveo U250, enabling hardware offload of multiple network protocols (TCP, RoCEv2).
- ▸Implemented PCIe/QDMA host ↔ FPGA communication using AXI-Stream in the OpenNIC 250 MHz user logic, allowing applications to drive FPGA transport logic.
- ▸Built buffering, backpressure, and request-framing logic to reliably inject host requests into a high-throughput FPGA networking pipeline.
Aug 2025 – PresentWaterloo, ON
Digital Design Team Lead — Ethernet Packet Parser
UW ASIC Design Team
- ▸Leading a team of 15 members on the architecture and RTL of a high-throughput Ethernet packet parser: a multi-layer pipeline for Ethernet/IP/TCP header extraction with configurable match-action rules, targeting 10G line rate.
- ▸Led RTL and floorplanning of a cryptography accelerator, closing timing at 200 MHz with 65% FPGA resource utilization.
Jan 2025 – May 2025Dubai, UAE
Software Engineer (Co-op)
VCast Online
- ▸Led full-stack development of a collaborative mind-map platform, enabling real-time feedback and map sharing, driving community engagement up by 25%.
- ▸Built and deployed a SvelteKit + Node.js web app integrating Cytoscape.js graph editing, Google OAuth, JWT authentication, and access control.
- ▸Architected a Mongoose-based feedback system enabling structured insights on nodes, edges, and graphs — improving data access times by 18%.
May 2024 – Aug 2024Waterloo, ON
Technical Writer (Co-op)
Dematic
- ▸Developed comprehensive technical documentation for Dematic's mechanical and control systems.
- ▸Authored detailed user manuals for Dematic's InSights logistics software, facilitating efficient deployment across multiple industries.
- ▸Simplified complex engineering concepts for diverse audiences, enhancing usability and efficiency.
Jan 2023 – Apr 2023Dorval, QC (Remote)
Technical Writer (Co-op)
Matrox Imaging | Zebra Technologies
- ▸Documented and tested new features for Matrox Design Assistant, a flowchart-based imaging application platform.
- ▸Collaborated with software engineers to document the Matrox Imaging Library (C API).
- ▸Used oXygen XML to update the official company user manual and user reference distributed to clients.
Education
Sep 2022 – Dec 2027Waterloo, ON
B.A.Sc. Computer Engineering
University of Waterloo
CoursesReconfigurable Computing (Master's), ML Hardware Systems (Master's), Computer Architecture, Digital Hardware Systems